Fetch-Execute Cycle

Fetch-Execute Cycle

This is the simplified version of the fetch-execute cycle outlining everything you would need to know for the A-Level computing exam.

Parts of the cycle

  • PC – Program Counter
  • MAR – Memory Address Register
  • MDR – Memory Data Register¬†(MBR -Memory Buffer Register)
  • CIR – Current Instruction Register
  • SR – Status Register
  • ACC – Accumulator
  • CU – Control Unit


This part of the cycle is illustrated above in an easy to understand diagram.

  1. The address location from the PC is fetched and copied into the MAR
  2. The contents of the memory location from the MAR is copied to the MDR
  3. The MDR is copied to the CIR
  4. The PC is incremented by 1
  5. The SR is checked for interuptions


  1. The instruction found in the CIR is interpreted by the decoder. (Decoded by the CPU’s CU)


  1. The instruction is split into Opcode and a operand.
  2. The address location from the instruction in the CIR is moved to the MAR
  3. The contents of the memory address location in the MAR is moved to the MDR
  4. The results of the computation stored in the MDR are moved to the ACC (Depends on the type of instruction, e.g. LOAD, ADD, STORE).
  5. SR is updated.

The cycle then repeats itself until there are no more instructions.